The present invention relates to the field of semiconductor integrated circuits. The invention is illustrated in an example with regard a semiconductor integrated circuit handling apparatus and method therefor, but it will be recognized that the invention will have a wider range of applicability. Merely by way of example, the invention may be also applied to testing packaged integrated circuit devices, assembly operations, and others.
Industry utilizes or has proposed a conventional method to manufacture a semiconductor integrated circuit. In particular, the conventional method includes the steps of fabrication, wafer sort, assembly, and test in that order. Fabrication forms the individual dies onto a semiconductor wafer. Each of the individual dies is tested to determine its operability, typically at wafer sort. Wafer sort also identifies good dies from bad dies also known as rejects. Bad dies are often marked by either a probe or ink mark at the wafer sort operation, typically either during the same or different operation. Assembly packages each good or un-marked integrated circuit device, and test electrically tests the integrated circuit device for operability and at times reliability.
The conventional approach to sort each wafer relies upon the use of a wafer handling apparatus such as a wafer prober and a tester, typically either memory, logic, mixed signal, or the like, depending upon the type of die being tested. A limitation of the wafer prober includes its inability to process a different and often larger sized wafer. The wafer prober typically designed with a certain stage dimension is not often capable of handling wafers having a dimension larger than its designed stage dimension. As wafers become larger, wafer probers which have larger sized stages must be purchased or stages of old wafer probers with smaller stages must be changed to accommodate the larger sized wafers.
Another limitation of the conventional wafer prober relates to the cost of each tester and prober combination. For example, the wafer sort process is often a "bottle-neck" operation, that is, enough product throughput capacity often does not exist at such operation with certain downtime or non-productive time. Typically the quantity of tester and prober pairs available at the sort operation rarely exceeds the amount often needed to sort the wafers being processed, that is, without excessive downtime. In particular, the manufacturer often does not purchase extra testers nor probers at the sort operation because of the high cost of each tester and prober pair, typically running in the millions of dollars. Accordingly, wafer prober output must be consistent, that is, without excessive downtime or non-productive time, to maintain product flow through the wafer sort operation.
A conventional wafer prober set-up operation often contributes to the amount of downtime or more generally non-productive time. Each wafer prober should be set-up before a production lot of wafers is run through it. In particular, prober set-up typically includes certain mechanical adjustments to a probe card and the wafer prober, and a variety of electrical tests used to ensure the reliability and quality of the tester and prober combination being used. As integrated circuits become denser and the amount of bonding pads being tested increases, set-up typically consumes even more time and becomes more difficult to perform efficiently and accurately. Thus, the amount of set-up time continues to increase, thereby increasing the amount of non-productive time on each wafer prober.
A further limitation with the convention wafer prober includes the index speed of the wafer stage. As wafers become larger, the size of the wafer stage also increases proportionately. The larger sized stage often indexes at a slower speed than a smaller stage, often having a smaller diameter and weight. The slower index speed corresponds to slower input and output of wafers to each wafer prober, and therefore reduces wafer prober throughput capability.
Still a further limitation with the conventional wafer prober is the probe mark or scratch mark or ink mark often used to identify bad or reject dies. Specifically, the process of forming the marks increases the amount of time at the wafer sort operation. In addition, depending upon the accuracy of the product set-up, miss-operations typically also occur during the ink or probe mark step, thereby reducing the accuracy of the die per wafer. Further, a subsequent pick and place operation which separates good dies from bad dies often cannot easily recognize either the probe or ink or scratch marks accurately. This often causes miscounts between the sort operation and the pick and place operation, typically in the assembly area.
Another limitation with the conventional wafer prober comes from the increased cost of setting up a larger clean room for each new prober generation. As wafer size increases in diameter, a typical wafer prober also increases in size, that is, the foot print (floor space occupied by the machine) of each machine becomes larger for each succeeding generation of probers. The larger foot print of each machine occupies more clean room area which has been increasing in costs.
Still another limitation of the conventional wafer prober comes from the inability to test different product types on the same machine. As product lines become more diversified, industry needs a way to process and in particular sort or probe different product types on each machine. However, convention wafer prober technology tends not to allow for tests to be easily performed on die of different product types. Accordingly, wafer probers are often set-up to test only a single product type. When tests for multiple product types are needed, manufacturers typically purchase additional probers and testers to probe and test the additional product line, and thereby increase the flexibility of the manufacturing line. Accordingly the conventional technique for processing more than one type of product often becomes costly by adding more machines and creates more maintenance problems, often associated with the different types of probers and testers.
Still further, another limitation with the conventional wafer sort process includes the inability to characterize and/or bin integrated circuits often by speed through the use of a wafer map and separate similar integrated circuits from others on a wafer by way of separate cassettes, frames, magazines, or the like. For example, the conventional wafer prober probes and tests each die on a wafer. But the use of such wafer prober process cannot separate the similar die within a single wafer. The die often become separated at saw and re-categorized by speed at test. An engineer at test simply has no easy way to determine the wafer coordinate or location of the die when it enters the test area.
From the above it is seen that an apparatus and method for testing semiconductor integrated circuits that is low cost, is reliable, is flexible, performs at a speed substantially independent of wafer size, and requires little maintenance are often desired.